Flip-flops are fundamental elements used in the design of digital circuits. In general, a D flip-flop has an input signal D and an output signal Q. The output signal stores the previous value of the input signal until the circuit is triggered by a clock signal at which point Q takes on the current value of D.
Reducing dynamic power is an important criteria in the design of integrated circuits. As clock frequencies are increased to provide enhanced operating speeds, the importance of reducing the power usage associated with switching transistors is emphasized. For example, in current designs, more than half of the total dynamic power is associated with the operation of flip-flops and the clock networks.
FIG. 1 shows one embodiment of a prior art D flip-flop 100 having a master-slave configuration. Inverter 102 samples the input signal D and outputs it through pass gate 104 to the master latch formed by a feedback loop between inverter 106 and tri-state inverter 108. At the rising edge of a clock signal, CK, pass gate 110 feeds the value stored in the master latch to the slave latch formed by inverter 112 and tri-state inverter 114. The value held in the slave latch is output through inverter 116 as the signal Q. As shown, pass gates 104 and 110 as well as tri-state inverters 108 and 114 are controlled by the clock signal CK and an inverse clock signal CKB, which may be generated from the clock signal by inverter 118.
The power consumption of D flip-flop 100 is directly related to the number of transistors that switch states with the clock signal. This is a primary source of dynamic power usage of the flip-flop and corresponds to the charging and discharging of the internal and output capacitance of the transistor gates. The switching power per clock cycle of a given circuit may be represented by Equation (1):Energy/transition=(Cload+Cinternal)*V2/2  (1)As will be appreciated, if the load capacitance is fixed, reducing the switching power, and correspondingly, the dynamic power, of a circuit requires a reduction in the capacitance of the internal nodes of the transistors comprising the circuit such as by reducing the number of switching operations.
Conventional methods for reducing the switching power involve clock-gating individual flip-flops within a circuit. However, these techniques significantly increase the complexity, and therefore cost, of the circuit. Further, the prior art clock-gating methods may also actually increase the dynamic power consumed when circuit activity is high, leading to greater power consumption as compared to non-gated flip-flops at corresponding activity levels.
Accordingly, what has been needed are systems and methods for implementing D flip-flops having reduced dynamic power. It would also be desirable to provide D flip-flops that provide the reduction in power without sacrificing accuracy or significantly slowing operation. Likewise, it would be desirable to provide reduced dynamic power consumption even at high activity levels. This specification discloses systems and methods for accomplishing these and other goals.